Optimal lnstruction Set Design through Adaptive Database Generation (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
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概要
- 論文の詳細を見る
This paper proposes a new method to design an optimal pipelined instruction set processor for ASIP development using a formal HW/SW codesign methodology. First, a HW/SW partitioning algorithm for selecting an optimal pipelined architecture is outlined. Then, an adaptive database approach is presented that enables to enhance the optimality of the design through very accurate estimation of the performance of a pipelined ASIP in the HW/SW partitioning process. The experimental results show that the proposed method is effective and efficient.
- 社団法人電子情報通信学会の論文
- 1996-03-25
著者
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Binh Nguyen
Department Of Information And Computer Sciences Toyohashi University Of Technology
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IMAI Masaharu
Department of Information and Computer Sciences, Toyohashi University of Technology
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SHIOMI Akichika
Department of Information and Computer Sciences, Toyohashi University of Technology
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HIKICHI Nobuyuki
Software Research Associates, Inc.
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Imai M
Graduate School Of Information Science Technology Osaka University
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Imai Masaharu
Department Of Information And Computer Sciences Toyohashi University Of Technology
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Shiomi A
Shizuoka Univ. Hamamatsu‐shi Jpn
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Shiomi Akichika
Department Of Computer Science Faculty Of Information Shizuoka University
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Hikichi Nobuyuki
Software Research Associates Inc.
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Imai Masaharu
Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka Univ
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