A Performance Optimization Method for Pipelined ASIPs in Consideration of Clock Frequency (Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
This paper proposes an ASIP performance optimization method taking clock frequency into account. The performance of an instruction set processor can be measured using the execution time of an application program, which can be determined by the clock cycles to perform the application program divided by the applied clock frequency. Therefore, the clock frequency should also be tuned in order to maximize the performance of the processor under the given design constraints. Experimental results show that the proposed method determines an optimal combination of FUs considering clock frequency.
- 社団法人電子情報通信学会の論文
- 1999-11-25
著者
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TAKEUCHI Yoshinori
Department of Media Science, Graduate School of Information Science, Nagoya University
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IMAI Masaharu
Department of Information and Computer Sciences, Toyohashi University of Technology
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Imai Masaharu
Department Of Information And Computer Sciences Toyohashi University Of Technology
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Takeuchi Y
Osaka Univ. Toyonaka‐shi Jpn
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SHINOHARA Katsuya
Department of Informatics and Mathematical Science, Graduate School of Engineering Science, Osaka Un
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OHTSUKI Norimasa
Department of Informatics and Mathematical Science, Graduate School of Engineering Science, Osaka Un
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Ohtsuki N
Hokkaido Univ. Sapporo‐shi Jpn
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Shinohara Katsuya
Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka Univ
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Takeuchi Yoshinori
Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka Univ
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Imai Masaharu
Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka Univ
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Imai Masaharu
Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka Univ
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