部分回路抽出によるトランスダクション法の大規模回路への応用

概要

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With the progress of VLSI technology and high competition between manufactures, requirements for rapid design of correct and efficient circuits are growing greater and greater. Automatic Design in this area has been researched for years. In order to verify and maintain a given circuit efficiently, keeping the size of the circuit small is essensial. Moreover, lessening the area of the circuit may spare chip area; lessening the level of the circuit may shorten the propogation time. As a logic optimization method, Transduction Method was proposed in 1970's. Many application showed that it was powerful optimizaiton tool. Especially after the introduction of BDD technology, Transduction Method can treat relatively large circuits with relatively low cost. However, like any other Boolean minimization mehtods, Transduction Method consume lots of memories. This restricts its usability, especially for Large Scale Circuits. Many subnetwork-based approaches have been proposed. But optimization result was greatly affected by the quality of the subnetwork. In this paper, we propose an algorithm of extraction for subnetwork suited for Transduction Method and experiment results show that this improvement expands its usability for large scale circuits largely.
一般社団法人情報処理学会の論文
1997-03-12