高性能 VLSI のクロック配線方式

概要

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Recent progress in VLSI microfabrication technology has brought about much faster transistors but larger wiring delays. This has had a significant effect on design technologies in that naive designs with little consideration on wiring delays have often resulted in VLSIs with unexpectedly poor performance as compared with the one using older technologies. This is caused by increased multi-stage gate delays and clock skews. Clock skew is defined as the difference of clock delays from a clock source to flip flops. Larger clock skew will reduce the tolerances of multi-stage gate delays and in worst cases, causes incorrect chip operations. Moreover, in a multi-chip system, clock delay difference among various chips has similar effect on the performance of the system. Therefore, the clock skew within a chip as well as the clock delay should be minimal at the same time. This paper describes a novel clock wiring system that assures minimal skew and minimal delay which will allow performance-driven VLSI design, combined with timing-driven placement and routing. The key technology is RC delay balancing and variable wire width clock routing to achieve zero-skew and minimal delay.
湘南工科大学の論文
1997-03-25