Design of Parallel Scrambler Applied to Digital Multiplexer

概要

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The multiplexing technique is frequently used to realize effective usage of transmission system. For precise transmission of such a multiplexed information, the scrambling technique is very useful to randomize the bit stream. There are two types of scramblers, i.e., one is serial scrambler and the other is parallell scrambler. Serial type is used for output multiplexed bit stream, therefore its operating speed becomes higher than input bit rate. On the other hand, since parallel scrambler which is applied to input bit stream operates as same as input bit rate, it is desirable on the standpoints of circuit configration and economics. But, its design method is not always enough, especially in the case of higher multiple numbers compared to the stage numbers of scrambler and word multiplexing method. This paper proposes the design method of parallel scrambler applied to digital multiplexer. It makes clear that output sequence of scrambler is simply obtained by introducing the recursive formulas which are constructed as linear sum of each shift resistor output and also proved that this method is available for the sequence which multiple numbers is higher than the stage numbers of scrambler. Furthermore, it can be extended to word multiplexing sequence, based on the method for bit multiplexing sequence.
東海大学の論文