A Harmonic-Free All Digital Delay-Locked Loop Using an Improved Fast-Locking Successive Approximation Register-Controlled Scheme
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概要
- 論文の詳細を見る
This paper proposes a novel delay-locked loop (DLL) with fast-locking property. The improved fast-locking successive approximation register-controlled (IFSAR) scheme can decrease the locking time to n+4 periods and be harmonic-free, where n is the bits number of the control code for a delay line. According to the simulation result in 180nm CMOS technology, the DLL can cover the operating range from 70MHz to 500MHz and dissipate 10.44mW at 500MHz.
- （社）電子情報通信学会の論文
- 2009-12-01
著者
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Shi Longxing
National ASIC Center, Southeast University
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CHEN Xin
National ASIC System Engineering Research Center, Southeast University
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Chen Xin
National Asic System Engineering Research Center Southeast University
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Shi Longxing
National Asic System Engineering Research Center Southeast University
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HUANG Kai
National ASIC System Engineering Research Center, Southeast University
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CAI Zhikuang
National ASIC System Engineering Research Center, Southeast University
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Cai Zhikuang
National Asic System Engineering Research Center Southeast University
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Huang Kai
National Asic System Engineering Research Center Southeast University
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SHI Longxing
National ASIC System Engineering Research Center, Southeast University
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