A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop
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概要
- 論文の詳細を見る
A novel fast lock-in digitally controlled phase-locked loop (DCPLL) is proposed in this letter. This DCPLL adopts a novel frequency search algorithm to reduce the lock-in time. Furthermore, to reduce the power consumption, the frequency divider is reused as a frequency detector during the frequency acquisition, and reused as a time-to-digital converter module during the phase acquisition. To verify the proposed algorithm and architecture, a DCPLL design is implemented by SMIC 0.18µm 1P6M CMOS technology. The Spice simulation results show that the DCPLL can achieve frequency acquisition in 3 reference cycles and complete phase acquisition in 11 reference cycles when locking to 200MHz. The corresponding power consumption of DCPLL is 3.71mW.
- （社）電子情報通信学会の論文
- 2008-12-01
著者
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Yang Jun
National Laboratory of Acoustics, Institute of Acoustics, Chinese Academy of Sciences
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Chen Xin
Southeast Univ. Chn
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CHEN Xin
National ASIC System Engineering Research Center, Southeast University
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SHI Long-xing
National ASIC System Engineering Research Center, Southeast University
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Chen Xin
National Asic System Engineering Research Center Southeast University
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Yang Jun
National Chromatographic R&a Center Dalian Institute Of Chemical Physics Chinese Academy Of Scie
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Yang Jun
Southeast Univ. Nanjing Chn
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Shi Long-xing
National Asic System Engineering Research Center Southeast University
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Yang Jun
National Asic System Engineering Research Center Southeast University
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