Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications

スポンサーリンク

概要

• 論文の詳細を見る

• This paper presents a novel architecture design to optimize the reconfiguration process of a coarse-grained reconfigurable architecture (CGRA) called Reconfigurable Multimedia System II (REMUS-II). In REMUS-II, the tasks in multi-media applications are divided into two parts: computing-intensive tasks and control-intensive tasks. Two Reconfigurable Processor Units (RPUs) for accelerating computing-intensive tasks and a Micro-Processor Unit (µPU) for accelerating control-intensive tasks are contained in REMUS-II. As a large-scale CGRA, REMUS-II can provide satisfying solutions in terms of both efficiency and flexibility. This feature makes REMUS-II well-suited for video processing, where higher flexibility requirements are posed and a lot of computation tasks are involved. To meet the high requirement of the dynamic reconfiguration performance for multimedia applications, the reconfiguration architecture of REMUS-II should be well designed. To optimize the reconfiguration architecture of REMUS-II, a hierarchical configuration storage structure and a 3-stage reconfiguration processing structure are proposed. Furthermore, several optimization methods for configuration reusing are also introduced, to further improve the performance of reconfiguration process. The optimization methods include two aspects: the multi-target reconfiguration method and the configuration caching strategies. Experimental results showed that, with the reconfiguration architecture proposed, the performance of reconfiguration process will be improved by 4 times. Based on RTL simulation, REMUS-II can support the 1080p@32fps of H.264 HiP@Level4 and 1080p@40fps High-level MPEG-2 stream decoding at the clock frequency of 200MHz. The proposed REMUS-II system has been implemented on a TSMC 65nm process. The die size is 23.7mm2 and the estimated on-chip dynamic power is 620mW.

• 2012-07-01

著者

• Shi Longxing

  National ASIC Center, Southeast University

• Liu Leibo

  Institute Of Microelectronics Tsinghua University

• Zhu Min

  Institute Of Microelectronics Tsinghua University

• Wei Shaojun

  Institute Of Microelectronics Tsinghua University

• Cao Peng

  National Asic System Engineering Research Center Southeast University

• Yang Jun

  National Asic System Engineering Research Center Southeast University

• ZHU Min

  Institute of Microelectronics, Tsinghua University

• WEI Shaojun

  Institute of Microelectronics, Tsinghua University

• YANG Jun

  National ASIC system Engineering Research Center, Southeast University

• LIU Bo

  National ASIC system Engineering Research Center, Southeast University

• Cao Peng

  National ASIC system and research engineering center, Southeast University

関連論文

• 2P2c-10 逐次最小2乗プレフィルタリングを用いるランダムアレイの最適時間反転集束法(ポスターセッション)
• Current reused Colpitts VCO and frequency divider with quadrature outputs
• Compositionally Bi-layered Formation of Interfacial Voids in a Porous Anodic Alumina Template Directly Formed on Si
• 2P2b-17 超音波顔識別システムの開発(ポスターセッション)
• A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop
• Discrimination of Type 2 diabetic patients from healthy controls by using metabonomics method based on their serum fatty acid profiles
• Compiler Framework for Reconfigurable Computing Architecture
• Memory-Efficient and High-Performance Two-Dimensional Discrete Wavelet Transform Architecture Based on Decomposed Lifting Algorithm
• Diagnosis of liver cancer using HPLC-based metabonomics avoiding false-positive result from hepatitis and hepatocirrhosis diseases
• A Harmonic-Free All Digital Delay-Locked Loop Using an Improved Fast-Locking Successive Approximation Register-Controlled Scheme
• Study on vibration effects of decked charge in bench blasting
• Metal-Organic Framework (MOF) as a Precursor for Synthesis of Platinum Supporting Zinc Oxide Nanoparticles
• A GC-based metabonomics investigation of type 2 diabetes by organic acids metabolic profile
• Determination of urinary nucleosides by direct injection and coupled-column high-performance liquid chromatography
• A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System
• Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System
• CropNET : A Wireless Multimedia Sensor Network for Agricultural Monitoring
• Integrated Current Sensing Technique Suitable for Step-Down Switch-Mode Power Converters
• Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications
• An optimized QFP structure for use in radio frequency multi-chip module applications
• Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture
• Fast AdaBoost-Based Face Detection System on a Dynamically Coarse Grain Reconfigurable Architecture
• Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC
• Multi-Battery Scheduling for Battery-Powered DVS Systems
• Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications
• Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture
• Handling Deafness Problem of Scheduled Multi-Channel Polling MACs
• Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC
• Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip
• Affine Transformations for Communication and Reconfiguration Optimization of Mapping Loop Nests on CGRAs
• A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures
• A novel DC-12GHz variable gain amplifier in InGaP/GaAs HBT technology
• Parallelization of Computing-Intensive Tasks of SIFT Algorithm on a Reconfigurable Architecture System
• An improved timing monitor for deep dynamic voltage scaling system
• A wide-range and ultra fast-locking all-digital SAR DLL without harmonic-locking
• The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture
• VLSI Design of a Reconfigurable S-box Based on Memory Sharing Method
• On-chip long-term jitter measurement for PLL based on undersampling technique
• An Inductive-Coupling Interconnected Application-Specific 3D NoC Design
• Battery-Aware Task Mapping for Coarse-Grained Reconfigurable Architecture
• Concurrent Detection and Recognition of Individual Object Based on Colour and p-SIFT Features
• A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures
• Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip
• Concurrent Detection and Recognition of Individual Object Based on Colour and p-SIFT Features

もっと見る 閉じる

スポンサーリンク