A wide-range and ultra fast-locking all-digital SAR DLL without harmonic-locking
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概要
- 論文の詳細を見る
A novel implementation of the complete all-digital M-b successive approximation register-controlled delay-locked loop (SAR DLL) is presented with wide-range, reduced hardware overhead and close to 50% duty cycle. The proposed SAR DLL adopts the digital-controlled resettable delay line to achieve the ultra fast-locking and eliminate the harmonic-locking issue of the conventional SAR ADDLL in wide-range application. All design units are first described in verilog, and then mapped to silicon using the SMIC 0.18µm CMOS Artisan standard cell library.
- The Institute of Electronics, Information and Communication Engineersの論文
著者
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Shi Longxing
National ASIC Center, Southeast University
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CAI Zhikuang
National ASIC System Engineering Research Center, Southeast University
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Cai Zhikuang
National Asic System Engineering Research Center Southeast University
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XU Tailong
School of Electronics and Information, Anhui University
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SUN Haiyan
National ASIC System Engineering Research Center, Southeast University
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