Inter-Layer Dielectric Reliability on 1GDRAM with COB Structure
スポンサーリンク
概要
- 論文の詳細を見る
- 1999-09-20
著者
-
Kim D.
Advanced Technology Development Semiconductor R&d Div. Samsung Electronics Co. Ltd
-
Kim J.
Advanced Technology Team 2 Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Park Y.
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
KIM B.
Semiconductor R&D Center, Samsung Electronics Co., Ltd.
-
KIM D.
Semiconductor R&D Center, Samsung Electronics Co., Ltd.
-
BAE M.
Semiconductor R&D Center, Samsung Electronics Co., Ltd.
-
NAM J.
Semiconductor R&D Center, Samsung Electronics Co., Ltd.
-
LEE S.
Semiconductor R&D Center, Samsung Electronics Co., Ltd.
-
KIM J.
Semiconductor R&D Center, Samsung Electronics Co., Ltd.
-
KIM T.
Semiconductor R&D Center, Samsung Electronics Co., Ltd.
-
PARK J.
Semiconductor R&D Center, Samsung Electronics Co., Ltd.
-
Lee S.
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kim J.
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kim D.
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Park J.
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kim T.
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kim T.
Semiconductor R&d Center Samsung Electronics Co. Ltd
-
Kim B.
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Lee S.
Semiconductor Advanced Research Div. Hyundai Electronics Industries Co.
-
Nam J.
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kim J.
Advanced Technology Development 2 Team Semiconductor R&d Center Memory Division Samsung Electron
-
Bae M.
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
PARK J.
Semiconductor R&D Center, Samsung Electronics Co., Ltd.
関連論文
- Optimization of Ring Type Electrode Process for High Density PRAM
- A Technology for Suppressing Inter-Layer Dielectric Crack in a High Density DRAM
- Suppression of Storage Node Contact Distortion for Gigabit-Scale DRAM with COB Structure
- Inter-Layer Dielectric Reliability on 1GDRAM with COB Structure
- Current Development Status and Future Challenge of FeRAM Technologies
- Endurance Characterization of Ferroelectric Cell in 64Mb FRAM Device By Analyzing the Space Charge Concentration
- Vacuum Bonding for the Fabrication of PBSOI
- Robust 2-D Stack Capacitor Technologies for 64Mb 1T1C FRAM
- Elimination of Al Line and Via Resistance Degradation under HTS Test in the Application of F-Doped Oxide as Intermetal Dielectrics
- A Novel T-Shaped Shallow Trench Isolation Technology Using Sidewall Spacer for 512Mbit Flash Memories and Beyond
- Cost-Effective and Highly Reliable 6F2 Multi-Gigabit DRAM in 60nm Technology Node for Low Power and High Performance Applications
- The Device Degradation Due to Contamination from STI Filling Material
- Low Damage In-Situ Contact Cleaning Method by a Highly Dense and Directional ECR Plasma
- Highly Manufacturable 64M bit Ultra Low Power SRAM Using a Novel 3-Dimensional S^3 (Stacked Single-crystal Si) Cell Technology
- High Performance Buried Channel-pFETs Using Elevated Source/Drain Structure with Self-Aligned Epitaxial Silicon Sliver (SESS)
- Stress Effect on the Reliability of pMOS TFTs for 16Mb SRAM : DC Stress at Room and Elevated Temperatures
- THE INFLUENCE OF INTEGRATION PROCESS ON THE IMPRINT IN PT-PZT-PT FERROELECTRIC CAPACITORS