Stress Effect on the Reliability of pMOS TFTs for 16Mb SRAM : DC Stress at Room and Elevated Temperatures
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概要
- 論文の詳細を見る
- 1995-08-21
著者
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Kim D.
Semiconductor R&d Center Samsung Electronics Co. Ltd.
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Kim D.
Semiconductor Research Laboratory Hyundai Electronics Industry Co. Ltd.
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Yoon H.
Semiconductor Research Laboratory Hyundai Electronics Industry Co. Ltd.
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SON K.
Semiconductor Research Laboratory, Hyundai Electronics Industry Co., LTD.
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LEE Y.
Semiconductor Research Laboratory, Hyundai Electronics Industry Co., LTD.
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AHN S.
Semiconductor Research Laboratory, Hyundai Electronics Industry Co., LTD.
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Son K.
Semiconductor Research Laboratory Hyundai Electronics Industry Co. Ltd.
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Lee Y.
Semiconductor Research And Development Laboratory Hyundai Electronics Industry Co. Ltd.
関連論文
- A Technology for Suppressing Inter-Layer Dielectric Crack in a High Density DRAM
- Suppression of Storage Node Contact Distortion for Gigabit-Scale DRAM with COB Structure
- Inter-Layer Dielectric Reliability on 1GDRAM with COB Structure
- Stress Effect on the Reliability of pMOS TFTs for 16Mb SRAM : DC Stress at Room and Elevated Temperatures
- Metal Node Contact TFT SRAM Cell for High Speed, Low Voltage Applications