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School of Electrical Eng. | 論文
- 24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization(Session8B: High-Frequency, Photonic and Sensing Devices)
- Extraction of Trap Depth in Flash Cell Having Arch-Active Structure
- Spatial Distribution of Channel Thermal Noise in Short-Channel MOSFETs
- Improving the Cell Characteristics Using SiN Liner at Active Edge in 4G NAND Flash
- Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- 24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization(Session8B: High-Frequency, Photonic and Sensing Devices)
- Non-Quasi-Static Small-Signal Model of RF MOSFETs Valid up to 110GHz
- ED2000-80 / SDM2000-80 MOS Memory Using Si Nanocrystals Formed by Wet Etching of Poly-Silicon Along Grain Boundaries
- Extraction of Vertical, Lateral Locations and Energies of Hot-Electrons-Induced Traps through the Random Telegraph Noise
- Improving the Cell Characteristics Using SiN Liner at Active Edge in 4 Gbits NAND Flash Memories
- Extraction of T-Type Substrate Resistance Components for Radio-Frequency Metal--Oxide--Semiconductor Field-Effect Transistors Based on Two-Port S-Parameter Measurement
- Simple Wide-Band Metal-Insulator-Metal (MIM) Capacitor Model for RF Applications and Effect of Substrate Grounded Shields
- Highly Manufacturable and Reliable 80-nm Gate Twin Silicon–Oxide–Nitride–Oxide–Silicon Memory Transistor
- Simultaneous Extraction of Locations and Energies of Two Independent Traps in Gate Oxide From Four-Level Random Telegraph Signal Noise
- Characterization of Sensitivity and Resolution of Silicon Resistive Probe
- Compact Current Modeling of Fully Depleted Symmetric Double-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Doped Short-Channel