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Renesas Technol. Corp. Itami‐shi Jpn | 論文
- 共蒸着保護層を用いたカラープラズマディスプレイの発光特性の改善とエージング特性
- Improvement of Luminous Efficiency in Barrier-Electrode Color ac Plasma Displays by Using a Double Protecting Layer
- A CAD-Compatible SOI-CMOS Gate Array Using 0.35 μm Partially-Depleted Transistors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
- 招待講演 A 65nm embedded SRAM with wafer level burn-in mode, leak-bit redundancy and E-trim fuse for known good die (集積回路)
- A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model
- A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures(Interconnect, VLSI Design and CAD Algorithms)
- A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs (Special Issue on Circuit Technologies for Memory and Analog LSIs)
- A Mixed-Mode Voltage Down Converter with Impedance Adjustment Circuitry for Low-Voltage High-Frequency Memories
- Selective-Sets Resizable Cache Memory Design for High-Performance and Low-Power CPU Core(Low-Power System LSI, IP and Related Technologies)
- A Low-Power Microcontroller with Body-Tied SOI Technology(Low-Power System LSI, IP and Related Technologies)
- Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation(the IEEE International Conference on SISPAD '02)
- Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations
- A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology
- Design and Performance of High T_c Superconducting Coplanar Waveguide Matching Circuit for RF-CMOS LNA(Special Issue on Superconductor Digital/Analog Circuit Technologies)
- Design and Performance of Miniaturized HTS Coplanar Waveguide Bandpass Filters with Highly Packed Meanderlines(Special Issue on Superconductive Electronics)
- Micromagnetic Simulation of Recording Media and Magnetoresistive Heads
- A Flexible Search Managing Circuitry for High-Density Dynamic CAMs (Speial Section on High Speed and High Density Multi Functional LSI Memories)
- A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories (Special Issue on LSI Memories)
- Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
- An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's(Special Issue on the 1994 VLSI Circuits Symposium)