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Device Development Center, Hitachi, Ltd. | 論文
- Significance of Ultra Clean Technology in the Era of ULSIs (Special Issue on Scientific ULSI Manufacturing Technology)
- Reducing Reverse-Bias Current in 450℃-Annealed n^+p Junction by Hydrogern Radical Sintering
- Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration(Dependable Computing)
- A Bipolar-Based 0.5μm BiCMOS Technology on Bonded SOI for High-Speed LSIs (Special Section on High Speed and High Density Multi Functional LSI Memories)
- Noise Reduction Techniques for a 64kb ECL-CMOS SRAM with a 2ns Cycle Time (Special Issue on LSI Memories)
- Redundancy Technique for Ultra-High-Speed Static RAMs
- Characterizing Film Quality and Electromigration Resistance of Giant-Grain Copper Interconnects (Special Issue on Sub-Half Micron Si Device and Process Technologies)
- Design of a 2-ns Cycle Time 72-kb ECL-CMOS SRAM Macro
- Redundancy Circuit for a Sub-nanosecond, Megabit ECL-CMOS SRAM
- A 0.65-ns, 72-kb ECL-CMOS RAM Macro for a 1-Mb SRAM(Special Issue on the 1994 VLSI Circuits Symposium)
- A 1.5-ns Cycle-Time 18-kb Pseudo-Dual-Port RAM with 9K Logic Gates (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- HCI-Free Selective Epitaxial SiGe Growth by LPCVD for 80-GHz BiCMOS Production
- Delay Library Generation with High Efficiency and Accuracy on the Basis of RSM (Special lssue on SISPAD'99)
- A 5 ns Cycle 1 Mb Synchronous SRAM with a Fast Write Technology (Special Issue on ULSI Memory Technology)
- Copper Wires for High Speed Logic LSI Prepared by Low Pressure Long Throw Sputtering Method
- Impact of Self-Aligned Metal Capping Method on Submicron Copper Interconnections
- A 120-MHz BiCMOS Superscalar RISC Processor (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- Analysis of Boron Penetration and Gate Depletion Using Dual-Gate PMOSFETs for High Performance G-Bit DRAM Design(Special Issue on Microelectronic Test Structures)
- Proposal for the Coma Aberration Dependent Overlay Error Compensation Technology
- Effects of 50 to 200-keV Electrons by BEASTLI Method on Semiconductor Devices (Special Issue on Scientific ULSI Manufacturing Technology)