A 5 ns Cycle 1 Mb Synchronous SRAM with a Fast Write Technology (Special Issue on ULSI Memory Technology)

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概要

• 論文の詳細を見る

• A GTL/LV-CMOS interfaced 1 M bit (32 k words × 36 bits/64 k words × 18 bits) BiCMOS cache SRAM is designed within a 5.65 × 10.54 mm^2 chip size. The process is 0.4μm BiCMOS with 4 poly-Si layers, 3 Metal layers, and TFT memory cells (2.66 × 4.94 μm^2). The late write operation is newly adopted. The late write operation method improvements make the fast access time 6 ns and the shorter cycle time 5 ns.

• 社団法人電子情報通信学会の論文
• 1996-06-25

著者

• Ohkuma S

  Elpida Memory Inc. Sagamihara‐shi Jpn

• Ichikawa H

  Ntt Corp. Yokosuka‐shi Jpn

• OHKUMA Sadayuki

  Device Development Center, Hitachi, Ltd.

• ICHIKAWA Hiroshi

  Device Development Center, Hitachi, Ltd.

• YUKUTAKE Seigo

  Semiconductor & Integrated Circuits Div, Hitachi, Ltd.

• END0 Hitoshi

  Hitachi ULSI Engineering

• KUB0UCHI Shuichi

  Hitachi ULSI Engineering

• Endo H

  Hitachi Ulsi Engineering

• Yukutake Seigo

  Semiconductor & Integrated Circuits Div Hitachi Ltd.

• Ichikawa Hiroshi

  Device Development Center Hitachi Ltd.

関連論文

• A 5 ns Cycle 1 Mb Synchronous SRAM with a Fast Write Technology (Special Issue on ULSI Memory Technology)
• A Centralized Control Microcell Radio System with Spectrum Delivery Switches (Special Issue on Fiber-optic Microcelluler Radio Communication System and Their Technologies)

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