Analysis of Boron Penetration and Gate Depletion Using Dual-Gate PMOSFETs for High Performance G-Bit DRAM Design(Special Issue on Microelectronic Test Structures)
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概要
- 論文の詳細を見る
We developed a method for analysis of boron penetration and gate depletion using N^+ and P^+ dual-gate PMOSFETs. An N^+ gate PMOSFETs, which is immune to boron penetration and gate depletion, exhibited the threshold voltage shifts and fluctuation in P^+ gate PMOSFETs fabricated using identical N^- substrates. We showed the importance of Vth fluctuation analysis and found that the Vth fluctuation in N^+ gate PMOSFETs was negligible, but, the Vth fluctuation in P^+ gate PMOSFETs was significant, indicating that the Vth fluctuation in P^+ gate PMOSFETs was dominated by boron penetration. It was also shown, for the first time, that boron penetration occurred with gate depletion, and gate depletion must be very strong to suppress boron penetration. The dual-gate PMOSFET method makes it possible to select high-performance G-bit DRAM fabrication processes that are robust against Vth fluctuation.
- 社団法人電子情報通信学会の論文
- 2002-05-01
著者
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Kimura Shunji
Ntt Network Innovation Laboratories
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YAMADA Satoru
ELPIDA MEMORY, Inc.
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KIMURA Shinichiro
Central Research Laboratory, Hitachi, Ltd
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Yamada S
Advanced Device Development Gr. Elpida Memory Inc.
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TAKAURA Norikatsu
Central Research Laboratory, Hitachi, Ltd.
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NAGAI Ryo
ELPIDA memory, Inc., Device Development Center, Hitachi, Ltd.
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ASAKURA Hisao
Device Development Center, Hitachi, Ltd.
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Asakura Hisao
Information & Control Systems Division Computer Systems Quality Assurance Section Hitachi Ltd.
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Kimura Shinichiro
Central Research Laboratory Hitachi. Ltd.
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Kimura Shinichiro
Central Research Laboratory Hitachi Ltd.
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Nagai Ryo
Elpida Memory Inc. Device Development Center Hitachi Ltd.
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Asakura Hisao
Device Development Center Hitachi Ltd.
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Takaura Norikatsu
Central Research Laboratory Hitachi. Ltd.
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Yamada Satoru
Elpida Memory Inc. Device Development Center Hitachi Ltd.
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Yamada Satoru
Elpida Memory Inc.
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