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Department of Information Systems Engineering, Osaka University | 論文
- Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling(Analog Circuits and Related SoC Integration Technologies)
- Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line(Interconnect,VLSI Design and CAD Algorithms)
- Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
- Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- Representative Frequency for Interconnect R(f)L(f)C Extraction(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- Experimental Study on Cell-Base High-Performance Datapath Design(IP Design)(VLSI Design and CAD Algorithms)
- Experimental Study on Cell-Base High-Performance Datapath Design
- Timing Analysis Considering Spatial Power/Ground Level Variation(Physical Design,VLSI Design and CAD Algorithms)
- JPM-Based Differential Image Storage Method for Image Revision Management System
- In Vitro Durability of One-bottle Resin Adhesives Bonded to Dentin
- Development of the Cavernous Sinus in the Fetal Period : A Morphological Study
- Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration
- Timing Analysis Considering Temporal Supply Voltage Fluctuation
- Prediction of Self-Heating in Short Intra-Block Wires
- Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
- Transistor Sizing of LCD Driver Circuit for Technology Migration(Circuit Synthesis,VLSI Design and CAD Algorithms)
- Crosstalk Noise Estimation for Generic RC Trees(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- Effects of On-Chip Inductance on Power Distribution Grid(VLSI Design and CAD Algorithms)
- Increase in Delay Uncertainty by Performance Optimization(Special Section on VLSI Design and CAD Algorithms)
- Statistical Analysis of Clock Skew Variation in H-Tree Structure(Prediction and Analysis, VLSI Design and CAD Algorithms)