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Department of Information Systems Engineering, Osaka University | 論文
- Crosstalk Noise Optimization by Post-Layout Transistor Sizing(Physical Design)(VLSI Design and CAD Algorithms)
- A Performance Prediction of Clock Generation PLLs : A Ring Oscillator Based PLL and an LC Oscillator Based PLL(Integrated Electronics)
- A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits
- Diabetic Mastopathy in an Advanced Elderly Woman with Insulin-Dependent Type 2 Diabetes Mellitus
- Performance Estimation at Architecture Level for Embedded Systems(Special Section on VLSI Design and CAD Algorithms)
- Low-Power VLSI Implementation by NMOS 4-Phase Dynamic Logic (特集 電子システムの設計技術と設計自動化)
- Low-Power Scheme of NMOS 4-Phase Dynamic Logic (Special Issue on Integrated Electronics and New System Paradigms)
- Repeated Intracerebral Hemorrhage Associated with Impaired Platelet Aggregation : Report of Two Cases
- Surgical Treatment of Endolymphatic Sac Tumor With Adjunctive Stereotactic Radiation Therapy-Case Report-
- Optical Wave-Band Switching Scheme and Its Wave-Band Design Method(Photonic IP Network Technologies for Next Generation Broadband Access)
- Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
- An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability
- Cellular response to dentin-bonding composite resins with dentin disks using the agar overlay method
- Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution
- A-4-32 Improvement of Direction of Arrival Estimation of Speech using Two-Channel Microphone Array with Angle Position Realignment
- Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation
- Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- Extracting Device-Parameter Variations with RO-Based Sensors
- Stress Probability Computation for Estimating NBTI-Induced Delay Degradation
- Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis