ISHII Kenichi | Electrotechnical Laboratory

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著作論文

Experimental Fabrication of XMOS Transistors Using Lateral Solid-Phase Epitaxy of CVD Silicon Films
Low-Temperature Pretreatment in Chemical Vapor Deposition of a Silicon Film for Solid-Phase Epitaxial Growth : Techniques, Instrumentations and Measurement
Fabrication of 40-150 nm Gate Length Ultrathin n-MOSFETs Using Epitaxial Layer Transfer SOI Wafers
Fabrication of 40-150nm Gate Length Ultrathin n-MOSFETs Using ELTRAN SOI Wafers
Fabrication of Nanometer-Scale Vertical Metal-Insulator-Metal Tunnel Junctions Using a Silicon-on-Insulator Substrate
Fabrication of Nanometer-Scale Vertical MIM Tunnel Junctions Using a Double-Layered Inorganic Resist
SiO_2/c-Si Bilayer Electron-Beam Resist Process for Nano-Fabrication
Evaluation of the Si-SiO_2 Interface by the Measurement of the Surface Recombination Velocity S by the Dual-Mercury Probe Method
Hydrogen Annealing of Transparent Gate MOS Diodes
A Low-Voltatge Alterable Metal-Oxide-Nitride-Oxide-Semiconductor Memory with Nano-Meter Thick Gate Insulators (NM-MONOS) : LATE NEWS
Optical Confinement in Thin Film Si Solar Cells by Diffuse Reflective Substrate
Sub-5μm Thin Film Crystalline Silicon Solar Cell on Alumina Ceramic Substrate

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