SOI/Bulk Hybrid Wafer Fabrication Process Using Selective Epitaxial Growth (SEG) Technique for High-End SoC Applications
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概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2003-04-30
著者
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MIZUSHIMA Ichiro
Process and Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation
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MIYANO Kiyotaka
Process and Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation
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SATO Tsutomu
Process and Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation
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Mizushima Ichiro
Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation
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Miyano Kiyotaka
Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation
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Nagano Hajime
Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation
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YAMADA Takashi
System LSI Research & Development Center, Semiconductor Company, Toshiba Corporation
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Sato Tsutomu
Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation
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Yamada Takashi
System Lsi Research & Development Center Semiconductor Company Toshiba Corporation
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MIZUSHIMA Ichiro
Process & Manufactruing Engineering Center, Semiconductor Company, Toshiba Corporation
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- Facet-Free Si Selective Epitaxial Growth Adaptable to Elevated Source/Drain MOSFETs with Narrow Shallow Trench Isolation
- Facet-Free Si Selective Epitaxial Growth Adaptable to Elevated Source/Drain MOSFETs with Narrow STI
- SOI/Bulk Hybrid Wafer Fabrication Process Using Selective Epitaxial Growth (SEG) Technique for High-End SoC Applications
- Formation of Ultrathin SiON Films on Si Substrates Having Different Orientations
- Defects Induced by Carbon Contamination in Low-Temperature Epitaxial Silicon Films Grown with Monosilane
- SOI/Bulk Hybrid Wafer Fabrication Process Using Selective Epitaxial Growth (SEG) Technique for High-End SoC Applications