High-Temperature Properties of Drain Current Variability in Scaled Field-Effect Transistors Analyzed by Decomposition Method

スポンサーリンク

概要

• 論文の詳細を見る

• The properties of drain current variability in field-effect transistors (FETs) at high temperature are experimentally investigated. It is found that the on-state drain current ($I_{\text{ON}}$) at high temperature has a strong correlation with $I_{\text{ON}}$ at room temperature and that there is no anomalous $I_{\text{ON}}$ change from room temperature to high temperature. It is also found that $I_{\text{ON}}$ variability at high temperature is smaller than that at room temperature. The origin of the decrease in $I_{\text{ON}}$ variability with increasing temperature is analyzed by the decomposition method developed in our previous work. It is clarified that the decrease in the current--onset voltage component plays a dominant role, especially in the saturation region. Moreover, it is also clarified that thermal excitation of carriers suppresses current--onset voltage variability, and ultimately the current--onset voltage component of $I_{\text{ON}}$ variability with increasing temperature.

• 2011-04-25

著者

• Terada Kazuo

  Faculty Of Information Sciences Hiroshima City University

• Kamohara Shiro

  Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete

• Kumar Anil

  Institute Of Industrial Science The University Of Tokyo

• Hiramoto Toshiro

  Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete

• Mogami Tohru

  Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete

• Nishida Akio

  Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete

• Inaba Satoshi

  Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete

• Mizutani Tomoko

  Institute Of Industrial Science The University Of Tokyo

• Tsunomura Takaaki

  Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete

• Takeuchi Kiyoshi

  Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete

• Kumar Anil

  Institute of Industrial Science, The University of Tokyo, Meguro, Tokyo 153-8505, Japan

• Inaba Satoshi

  Robust Transistor Program, NSI Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan

• Nishida Akio

  Robust Transistor Program, NSI Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan

• Mogami Tohru

  Robust Transistor Program, NSI Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan

• Kamohara Shiro

  Robust Transistor Program, NSI Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan

• Takeuchi Kiyoshi

  Robust Transistor Program, NSI Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan

• KUMAR Anil

  Institute Industrial Science, The University of Tokyo

関連論文

• Random Threshold Voltage Variability Induced by Gate-Edge Fluctuations in Nanoscale Metal-Oxide-Semiconductor Field-Effect Transistors
• Implementation of the Multicolored SOR Method on a Vector Supercomputer (Special Issue on Parallel and Distributed Supercomputing)
• High-Temperature Properties of Drain Current Variability in Scaled Field-Effect Transistors Analyzed by Decomposition Method
• Origin of Larger Drain Current Variability in N-Type Field-Effect Transistors Analyzed by Variability Decomposition Method
• Three-Dimensional Structure Analysis of Metal-Oxide-Insulator Field Effect Transistors with Different Electrical Properties by Scanning Transmission Electron Microscopy
• Test Circuit for Evaluating Characteristics Mismatch in Metal–Oxide–Semiconductor Field-Effect Transistor Pairs by Estimating Conductance Variation through Voltage Measurement
• Investigation of Threshold Voltage Variability at High Temperature Using Takeuchi Plot
• Suppression of Within-Device Variability in Intrinsic Channel Tri-Gate Silicon Nanowire Metal-Oxide-Semiconductor Field-Effect Transistors (Special Issue : Solid State Devices and Materials (1))
• Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors
• Verification of Threshold Voltage Variation of Scaled Transistors with Ultralarge-Scale Device Matrix Array Test Element Group
• Effect of Channel Dopant Non-uniformity on Transconductance Variability
• Statistical Analysis of Subthreshold Swing in Fully Depleted Silicon-on-Thin-Buried-Oxide and Bulk Metal--Oxide--Semiconductor Field Effect Transistors
• Possible Origins of Extra Threshold Voltage Variability in N-Type Field-Effect Transistors by Intentionally Changing Process Conditions and Using Takeuchi Plot
• Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress
• Statistical Analysis of Current Onset Voltage (COV) Distribution of Scaled MOSFETs
• NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM
• Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells

もっと見る 閉じる

スポンサーリンク