Verification of Threshold Voltage Variation of Scaled Transistors with Ultralarge-Scale Device Matrix Array Test Element Group

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概要

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• Randomness of threshold voltage ($V_{\text{T}}$) variations of negative channel field effect transistors (NFETs) and positive channel field effect transistors (PFETs) in the 65 nm technology is precisely examined. For this purpose, an ultralarge-scale device matrix array test element group (DMA-TEG) that contains 1 million single-size metal–oxide–semiconductor field-effect transistors (MOSFETs) has been designed and fabricated, and a very rapid measurement system has been developed. By evaluating $V_{\text{T}}$ of a very large number of MOSFETs, $V_{\text{T}}$ variation can be precisely evaluated. This rapid measurement is achieved by parallel address signal input, optimization of the measurement program, and 4-chip parallel measurements. The measured $V_{\text{T}}$ variations are decomposed into random and systematic components. The results reveal that the random component is overwhelmingly dominant in the $V_{\text{T}}$ variations in the 65 nm technology and that the $V_{\text{T}}$ variations exhibit a normal distribution up to $\pm 5\sigma$.

• 2009-12-25

著者

• Hiramoto Toshiro

  Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete

• Nishida Akio

  Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete

• Tsunomura Takaaki

  Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete

• Nishida Akio

  Robust Transistor Program, NSI Project, Research Dept. 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan

• Hiramoto Toshiro

  Robust Transistor Program, NSI Project, Research Dept. 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan

• Tsunomura Takaaki

  Robust Transistor Program, NSI Project, Research Dept. 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan

関連論文

• Random Threshold Voltage Variability Induced by Gate-Edge Fluctuations in Nanoscale Metal-Oxide-Semiconductor Field-Effect Transistors
• High-Temperature Properties of Drain Current Variability in Scaled Field-Effect Transistors Analyzed by Decomposition Method
• Origin of Larger Drain Current Variability in N-Type Field-Effect Transistors Analyzed by Variability Decomposition Method
• Three-Dimensional Structure Analysis of Metal-Oxide-Insulator Field Effect Transistors with Different Electrical Properties by Scanning Transmission Electron Microscopy
• Investigation of Threshold Voltage Variability at High Temperature Using Takeuchi Plot
• Verification of Threshold Voltage Variation of Scaled Transistors with Ultralarge-Scale Device Matrix Array Test Element Group
• Possible Origins of Extra Threshold Voltage Variability in N-Type Field-Effect Transistors by Intentionally Changing Process Conditions and Using Takeuchi Plot

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