Investigation of Threshold Voltage Variability at High Temperature Using Takeuchi Plot

概要

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The property of metal–oxide–semiconductor field-effect transistors’ (MOSFETs) threshold voltage ($V_{\text{T}}$) variability at high temperature is investigated by evaluating the device matrix array test element group (DMA-TEG). It is revealed that $V_{\text{T}}$ variation is lower at high temperature than at room temperature, and that $V_{\text{T}}$ at high temperature has a strong correlation with $V_{\text{T}}$ at room temperature. The normal property of $V_{\text{T}}$ variability both at room and high temperatures is validated using the normal probability plot. The decrease in $V_{\text{T}}$ variation at high temperature stems from the reduction of the channel depletion layer width ($W_{\text{dep}}$). The temperature dependence of $V_{\text{T}}$ variation is evaluated using the Takeuchi plot, the $V_{\text{T}}$ variation normalization method. It is revealed that the change in $B_{\text{VT}}$, the parameter of $V_{\text{T}}$ variation in the Takeuchi plot, is very small with varying temperature.
2010-05-25