Mizutani Tomoko | Institute Of Industrial Science The University Of Tokyo
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概要
関連著者
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Mizutani Tomoko
Institute Of Industrial Science The University Of Tokyo
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Hiramoto Toshiro
Institute Of Industrial Science The University Of Tokyo
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KUMAR Anil
Institute Industrial Science, The University of Tokyo
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HIRAMOTO Toshiro
Institute Industrial Science, The University of Tokyo
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Kumar Anil
Institute Of Industrial Science The University Of Tokyo
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Terada Kazuo
Faculty Of Information Sciences Hiroshima City University
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Kamohara Shiro
Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete
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Hiramoto Toshiro
Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete
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Mogami Tohru
Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete
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Nishida Akio
Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete
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Inaba Satoshi
Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete
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Tsunomura Takaaki
Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete
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Takeuchi Kiyoshi
Robust Transistor Program Nano Silicon Integration Project Research Department 4 Mirai-selete
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Hiramoto Toshiro
Institute Of Industrial Science University Of Tokyo
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Kamohara Shiro
Mirai-selete
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NISHIDA Akio
MIRAI-Selete
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Hiramoto Toshiro
The Authors Are With Institute Of Industrial Science The University Of Tokyo:the Author Is With Vlsi
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Hiramoto Toshiro
Vlsi Design And Education Center The University Of Tokyo:institute Of Industrial Science The Univers
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Hiramoto Toshiro
Inst. Of Industrial Science And Cinqie University Of Tokyo
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Hiramoto Toshiro
Vlsi Design And Education Center The University Of Tokyo
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Tsunomura Takaaki
Robust Transistor Program, Nano Silicon Integration Project, Research Department 4, MIRAI--Selete, T
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Mizutani Tomoko
Institute of Industrial Science, The University of Tokyo, Meguro, Tokyo 153-8505, Japan
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Nishida Akio
Robust Transistor Program, Nano Silicon Integration Project, Research Department 4, MIRAI--Selete, T
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Takeuchi Kiyoshi
Robust Transistor Program, Nano Silicon Integration Project, Research Department 4, MIRAI--Selete, T
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Inaba Satoshi
Robust Transistor Program, Nano Silicon Integration Project, Research Department 4, MIRAI--Selete, T
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Kumar Anil
Institute of Industrial Science, The University of Tokyo, Meguro, Tokyo 153-8505, Japan
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Inaba Satoshi
Robust Transistor Program, NSI Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan
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Nishida Akio
Robust Transistor Program, NSI Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan
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Mogami Tohru
Robust Transistor Program, NSI Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan
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Kamohara Shiro
Robust Transistor Program, NSI Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan
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Takeuchi Kiyoshi
Robust Transistor Program, NSI Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan
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Yamamoto Yoshiki
Low-power Electronics Association and Project (LEAP), Tsukuba, Ibaraki 305-8569, Japan
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Makiyama Hideki
Low-power Electronics Association and Project (LEAP), Tsukuba, Ibaraki 305-8569, Japan
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Iwamatsu Toshiaki
Low-power Electronics Association and Project (LEAP), Tsukuba, Ibaraki 305-8569, Japan
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Oda Hidekazu
Low-power Electronics Association and Project (LEAP), Tsukuba, Ibaraki 305-8569, Japan
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Sugii Nobuyuki
Low-power Electronics Association and Project (LEAP), Tsukuba, Ibaraki 305-8569, Japan
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Mao Ke
Institute of Industrial Science, University of Tokyo, Meguro, Tokyo 153-8505, Japan
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SARAYA Takuya
Institute Industrial Science, The University of Tokyo
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MIZUTANI Tomoko
Institute of Industrial Science, The University of Tokyo
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Mizutani Tomoko
Institute of Industrial Science, University of Tokyo, Meguro, Tokyo 153-8505, Japan
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HIRAMOTO Toshiro
Institute of Industrial Science, The University of Tokyo
著作論文
- High-Temperature Properties of Drain Current Variability in Scaled Field-Effect Transistors Analyzed by Decomposition Method
- Origin of Larger Drain Current Variability in N-Type Field-Effect Transistors Analyzed by Variability Decomposition Method
- Suppression of Within-Device Variability in Intrinsic Channel Tri-Gate Silicon Nanowire Metal-Oxide-Semiconductor Field-Effect Transistors (Special Issue : Solid State Devices and Materials (1))
- Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors
- Statistical Analysis of Subthreshold Swing in Fully Depleted Silicon-on-Thin-Buried-Oxide and Bulk Metal--Oxide--Semiconductor Field Effect Transistors
- Statistical Analysis of Current Onset Voltage (COV) Distribution of Scaled MOSFETs
- Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells