Study on Nano Complementary Metal Oxide Semiconductor Gate Leakage Current

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概要

• 論文の詳細を見る

• This work examines different components of the leakage current in scaled N and P-metal oxide semiconductor field-effect transistor (MOSFET) with ultra thin gate oxide. Experimental results show that the gate tunneling leakage current through the source/drain extension region (also named edge direct tunneling, EDT) is the largest component, which dominates the maximum off-state power consumption of a nano-scaled transistor. To clarify the relationship between this largest leakage component and the size of the source/drain to gate overlap region, the proposed capacitance–ratio method (C–R method) was used to precisely extract the dimensions of the source/drain to gate overlap, $L_{\text{ov}}$. To reduce the gate-tunneling leakage at the source/drain edge, a modified gate dielectric structure is proposed and verified in this work.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2003-05-15

著者

• Wu Yen-ching

  Institute Of Automation Technology National Taipei University Of Technology

• Hong Gary

  Central Integration United Microelectronics Corporation

• Huang Chia-hung

  Institute Of Mechatronics National Taipei University Of Technology

• Huang Heng-sheng

  Institute Of Automation Technology National Taipei University Of Technology

• Chen Jeng-Kang

  Central Research/Development, United Microelectronics Corporation, Hsin-Chu, Taiwan, R.O.C.

• Huang Chia-Hung

  Institute of Mechatronics, National Taipei University of Technology, Taipei, Taiwan, R.O.C.

• Hsu Yao-Kai

  Central Integration, United Microelectronics Corporation, Hsin-Chu, Taiwan, R.O.C.

• Hong Gary

  Central Integration, United Microelectronics Corporation, Hsin-Chu, Taiwan, R.O.C.

• Huang Heng-Sheng

  Institute of Mechatronics, National Taipei University of Technology, Taipei, Taiwan, R.O.C.

関連論文

• A Capacitance Ratio Method Used for L_ Extraction of an Advanced Metal-Oxide-Semiconductor Device with Halo Implant
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• Interfacial and Electrical Characterization in Metal–Oxide–Semiconductor Field-Effect Transistors with CeO2 Gate Dielectric
• Dual Fiber-Optic Fabry–Perot Interferometer Temperature Sensor with Low-Cost Light-Emitting Diode Light Source
• Behavior of Nano-N-Channel Metal–Oxide–Semiconductor Off-State Leakage Currents
• Study on Nano Complementary Metal Oxide Semiconductor Gate Leakage Current
• A Modified Capacitance–Voltage Method Used for $L_{\text{eff}}$ Extraction and Process Monitoring in Advanced 0.15 $\mu$m Complementary Metal-Oxide-Semiconductor Technology and Beyond
• Performance and Reliability Improvement of Low-Power Embedded Flash Memory with Shallow Trench Isolation Structure

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