Performance and Reliability Improvement of Low-Power Embedded Flash Memory with Shallow Trench Isolation Structure
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概要
- 論文の詳細を見る
The design of programming/erasing (P/E) coupling ratios of advanced low-power embedded flash cells (working as an on/off switch) with a shallow trench isolation (STI) structure has been discussed to meet future performance requirement. The reason that the stress-induced reliability degradation (SIRD) problem becomes more severe when the STI structure is used in a low-power flash cell has also been clearly explained. In this paper, we suggest a drain (or source) side erase method for both lower-voltage operation and quick data writing. This device must be operated at a suitable bias condition to achieve the best reliability. For further improvement in the control and uniformity of the reliability performance, a modified STI module and modified cell drain side engineering are proposed and verified on a 256 K NOR-type embedded low-power flash test vehicle.
- INSTITUTE OF PURE AND APPLIED PHYSICSの論文
- 2001-02-15
著者
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Hong Gary
Specialty Technology Division United Microelectronics Corporation
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Huang Heng-sheng
Institute Of Automation Technology National Taipei University Of Technology
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Lin Chih-hung
Specialty Technology Division United Microelectronics Corporation
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Su Jason
Institute Of Mechatronics National Taipei University Of Technology
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Ting Wen-chi
Specialty Technology Division United Microelectronics Corporation
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Lee Dong-lung
Institute Of Mechatronics National Taipei University Of Technology
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Lin Chih-Hung
Specialty Technology Division, United Microelectronics Corporation, Hsin-Chu, Taiwan, R.O.C.
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Ting Wen-Chi
Specialty Technology Division, United Microelectronics Corporation, Hsin-Chu, Taiwan, R.O.C.
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