上流設計工程でのサイドチャネル攻撃に対する耐タンパ検証手法とその評価

概要

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Recently, side-channel attacks have become a serious problem. These attacks estimate secret keys of cryptography circuits embedded in hardware. In particular, the most threatening side-channel attacks are differential power analysis and correlation power analysis that use the correlation between information processing and power consumption, which are related to secret keys in cryptography circuits. Therefore, new measures are required to prevent confidential information in cryptography circuits from being leaked to side-channel information, such as power consumption. When designing preventive measures, resistance to side-channel attacks, i.e., tamper resistance, must be evaluated. This study proposes a new simulation method by which tamper resistance can be verified in the algorithm and architecture design phases. Experimental results show the validity of the proposed simulation method.
社団法人電気学会の論文