電流モードMVD-ORNSの低消費電力化に関する考察

概要

論文の詳細を見る
Recently, advanced digital signal processing is necessary so that industry related to multimedia may develop. Because many arithmetic circuits are used in signal processing of the multimedia, a low-power and high-speed adder, which is basic element of the arithmetic circuits, are desired. On the other hand, multiple-valued digits overlap resolution number system (MVD-ORNS) was proposed in our lab, and is one of the number systems that make it possible to add in parallel. However, the hardware of MVD-ORNS consumes very large power. In this thesis, I design and analyze the very low-power MOS circuit elements, which are current-mirrors, switched current mirrors, etc. based on the weakinversion region, for the low-power MVD-ORNS. Finally, an 8-bit adder based on MVD-ORNS using the proposed circuits is designed. All of the proposed circuits are evaluated through HSPICE simulation with 0.35μm CMOS device parameters. The results are reported in this thesis.
宮崎大学の論文
2007-08-30