低電源電圧・広帯域CMOSアナログ乗算器の設計と2.4GHz RFダウンコンバージョンミキサへの応用

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Abstract In recent years, the world of wireless communications has been changing very rapidly. The wireless communication devices need RF analog circuits such as mixer. In CMOS technology, if it successfully merges RF analog and baseband digital blocks, it is possible to reduce size, weight,cost, and power consumption. However, the circuit elements which can be operated under low supply voltage are required because of lowering of the breakdown voltage with the development of fabrication technique in CMOS process. In this paper, a low-supply-voltage and wide-bandwidth CMOS analog multiplier is proposed, which is indispensable for mixer. The proposed multiplier has advantages of low voltage operation and low noise. Simulations of the multiplier demonstrate the input range of 0.54 Vp-p, the -3 dB bandwidth of 1.03 GHz and the S/N ratio of 131 dB with VDD=2 V. Next, the proposed multiplier is applied to a downconversion mixer. The mixer can be operated at VDD=2V, and the conversion gain and 3rd order intcrcept point (IIP3) are -O.8 dR and +10.9 dBm, respectively.
宮崎大学の論文