Hazard Checking of Asynchronous Circuits : A New Approach(高信頼アルゴリズム,ディペンダブルコンピュータシステムとセキュリティ技術及び一般)

スポンサーリンク

概要

• 論文の詳細を見る

• We present a new framework to express the semantics of asynchronous circuits, and as an application, an algorithm that will check an implementation given as a netlist against a specification given as a state graph (SG). The algorithm is based on an exploration of the specification that computes certain information (as symbolic states) about the corresponding implementation states, which information is represented as a boolean formula. The algorithm is efficient, can be easily extended so as to use timing informations, and in case of hazards, can provide the user with extensive and easy-to-use information about the cause of the hazard. While it induces potential conservativeness, we did not encounter such examples of false negatives.

• 社団法人電子情報通信学会の論文
• 2006-04-07

著者

• Myers Chris

  University Of Utah

• BEAL Frederic

  Tokyo Institute of Technology

• YONEDA Tomohiro

  National Institute of Informatics

• Yoneda Tomohiro

  National Inst. Of Informatics Tokyo Jpn

関連論文

• Hazard Checking of Asynchronous Circuits : A New Approach(高信頼アルゴリズム,ディペンダブルコンピュータシステムとセキュリティ技術及び一般)
• Hazard Checking of Asynchronous Circuits: A New Approach(高信頼アルゴリズム,ディペンダブルコンピュータシステムとセキュリティ技術及び一般)
• Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation(Dependable Computing)
• Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model(Verification and Dependability Analysis)(Dependable Computing)
• Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model
• Modular Synthesis of Timed Circuits Using Partial Order Reduction
• 時間付き信号遷移グラフの効率的縮約について(VLSIの設計/検証/テスト及び一般(デザインガイア))
• 時間付き信号遷移グラフの効率的縮約について(VLSIの設計/検証/テスト及び一般(デザインガイア))
• 時間付き信号遷移グラフの効率的縮約について(VLSIの設計/検証/テスト及び一般(デザインガイア))
• 時間付き信号遷移グラフの効率的縮約について(VLSIの設計/検証/テスト及び一般(デザインガイア))
• A Conservative Framework for Safety-Failure Checking
• Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times(System Level Design,VLSI Design and CAD Algorithms)
• A Case Study on Dependable Network-on-Chip Platform for Automotive Applications
• A Case Study on Dependable Network-on-Chip Platform for Automotive Applications
• Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits(Dependable Computing)
• Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol
• Comparison of standard cell based non-linear asynchronous pipelines (ディペンダブルコンピューティング)
• Comparison of standard cell based non-linear asynchronous pipelines (システムLSI設計技術・デザインガイア2007--VLSI設計の新しい大地を考える研究会)
• Framework of Timed Trace Theoretic Verification Revisited(Special Issue on Test and Verification of VLSI)
• Comparison of standard cell based non-linear asynchronous pipelines (VLSI設計技術)
• An Online Routing Mechanism with Higher Fault-Tolerance for Network-on-Chip
• Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories
• A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation

もっと見る 閉じる

スポンサーリンク