Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model(Verification and Dependability Analysis)(<Special Issue>Dependable Computing)
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概要
- 論文の詳細を見る
Using a level oriented model for verification of asynchronous circuits helps users to easily construct formal models with high readability or to naturally model data-path circuits. On the other hand, in order to use such a model for larger circuit, some technique to avoid the state explosion problem is essential. This paper first defines a level oriented formal model based on time Petri nets, and then proposes a partial order reduction algorithm that prunes unnecessary state generation while guaranteeing the correctness of the verification.
- 社団法人電子情報通信学会の論文
- 2003-12-01
著者
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Myers C
Univ. Utah Ut Usa
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Myers Chris
Department Of Electrical And Computer Engineering University Of Utah
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YONEDA Tomohiro
National Institute of Informatics
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KITAI Tomoya
Graduate School of Information Science and Engineering, Department of Computer Science, Tokyo Instit
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YONEDA Tomohiro
Infrastructure Systems Research Division, National Institute of Informatics
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OGURO Yusuke
Graduate School of Information Science and Engineering, Dept. of Computer Science, Tokyo Institute o
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MERCER Eric
Brigham Young University
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Yoneda T
Soka Univ. Hachioji‐shi Jpn
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Kitai Tomoya
Graduate School Of Information Science And Engineering Department Of Computer Science Tokyo Institut
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Oguro Yusuke
Graduate School Of Information Science And Engineering Dept. Of Computer Science Tokyo Institute Of
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Yoneda T
Infrastructure Systems Research Division National Institute Of Informatics
関連論文
- Hazard Checking of Asynchronous Circuits : A New Approach(高信頼アルゴリズム,ディペンダブルコンピュータシステムとセキュリティ技術及び一般)
- Hazard Checking of Asynchronous Circuits: A New Approach(高信頼アルゴリズム,ディペンダブルコンピュータシステムとセキュリティ技術及び一般)
- Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation(Dependable Computing)
- Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model(Verification and Dependability Analysis)(Dependable Computing)
- Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model
- Modular Synthesis of Timed Circuits Using Partial Order Reduction
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