Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits(Dependable Computing)
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概要
- 論文の詳細を見る
This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits efficiently. This algorithm is based on the framework of timed trace theoretic verification according to the original untimed trace theory. Consequently, its conformance checking supports hierarchical structure when verifying timed circuits. Experimenting with the STARI and DME circuits, the proposed approach shows its effectiveness.
- 社団法人電子情報通信学会の論文
- 2005-07-01
著者
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Myers Chris
Department Of Electrical And Computer Engineering University Of Utah
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YONEDA Tomohiro
National Institute of Informatics
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Yoneda Tomohiro
National Inst. Of Informatics Tokyo Jpn
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PRADUBSUWUN Denduang
Tokyo Institute of Technology
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