A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation

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概要

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• This paper proposes a behavioral synthesis system for asynchronous circuits with bundled-data implementation. The proposed system is based on a behavioral synthesis method for synchronous circuits and extended on operation scheduling and control synthesis for bundled-data implementation. The proposed system synthesizes an RTL model and a simulation model from a behavioral description specified by a restricted C language, a resource library, and a set of design constraints. This paper shows the effectiveness of the proposed system in terms of area and latency through comparisons among bundled-data implementations synthesized by the proposed system, synchronous counterparts, and bundled-data implementations synthesized by using a behavioral synthesis method for synchronous circuits directly.

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著者

• Yoneda Tomohiro

  National Inst. Of Informatics Tokyo Jpn

• HAMADA Naohiro

  The University of Aizu

• SAITO Hiroshi

  The University of Aizu

• Myers Chris

  The University of Utah

• Konishi Takao

  The University of Aizu

• Shiga Yuki

  The University of Aizu

• Nanya Takashi

  The University of Tokyo

関連論文

• Hazard Checking of Asynchronous Circuits : A New Approach(高信頼アルゴリズム,ディペンダブルコンピュータシステムとセキュリティ技術及び一般)
• Hazard Checking of Asynchronous Circuits: A New Approach(高信頼アルゴリズム,ディペンダブルコンピュータシステムとセキュリティ技術及び一般)
• Modular Synthesis of Timed Circuits Using Partial Order Reduction
• A Conservative Framework for Safety-Failure Checking
• Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times(System Level Design,VLSI Design and CAD Algorithms)
• A Case Study on Dependable Network-on-Chip Platform for Automotive Applications
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• Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol
• Comparison of standard cell based non-linear asynchronous pipelines (ディペンダブルコンピューティング)
• Comparison of standard cell based non-linear asynchronous pipelines (システムLSI設計技術・デザインガイア2007--VLSI設計の新しい大地を考える研究会)
• Framework of Timed Trace Theoretic Verification Revisited(Special Issue on Test and Verification of VLSI)
• Comparison of standard cell based non-linear asynchronous pipelines (VLSI設計技術)
• An Online Routing Mechanism with Higher Fault-Tolerance for Network-on-Chip
• Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation
• Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories
• A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation

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