A Conservative Framework for Safety-Failure Checking

スポンサーリンク

概要

論文の詳細を見る
2008-03-01

著者

関連論文

Hazard Checking of Asynchronous Circuits : A New Approach(高信頼アルゴリズム,ディペンダブルコンピュータシステムとセキュリティ技術及び一般)
Hazard Checking of Asynchronous Circuits: A New Approach(高信頼アルゴリズム,ディペンダブルコンピュータシステムとセキュリティ技術及び一般)
Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation(Dependable Computing)
Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model(Verification and Dependability Analysis)(Dependable Computing)
Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model
Modular Synthesis of Timed Circuits Using Partial Order Reduction
A Conservative Framework for Safety-Failure Checking
Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times(System Level Design,VLSI Design and CAD Algorithms)
A Case Study on Dependable Network-on-Chip Platform for Automotive Applications
A Case Study on Dependable Network-on-Chip Platform for Automotive Applications
Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits(Dependable Computing)
Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol
Comparison of standard cell based non-linear asynchronous pipelines (ディペンダブルコンピューティング)
Comparison of standard cell based non-linear asynchronous pipelines (システムLSI設計技術・デザインガイア2007--VLSI設計の新しい大地を考える研究会)
Framework of Timed Trace Theoretic Verification Revisited(Special Issue on Test and Verification of VLSI)
Comparison of standard cell based non-linear asynchronous pipelines (VLSI設計技術)
An Online Routing Mechanism with Higher Fault-Tolerance for Network-on-Chip
Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories
A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation

もっと見る

スポンサーリンク