Framework of Timed Trace Theoretic Verification Revisited(Special Issue on Test and Verification of VLSI)
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概要
- 論文の詳細を見る
This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.
- 社団法人電子情報通信学会の論文
- 2002-10-01
著者
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Myers Chris
Department Of Electrical And Computer Engineering University Of Utah
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YONEDA Tomohiro
National Institute of Informatics
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Yoneda Tomohiro
National Inst. Of Informatics Tokyo Jpn
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ZHOE Bin
Cadence Design Systems
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