YONEDA Tomohiro | National Institute of Informatics

スポンサーリンク

概要

• YONEDA Tomohiroの詳細を見る
• 同名の論文著者
• National Institute of Informaticsの論文著者

関連著者

• YONEDA Tomohiro

  National Institute of Informatics

• Yoneda Tomohiro

  National Inst. Of Informatics Tokyo Jpn

• Myers Chris

  Department Of Electrical And Computer Engineering University Of Utah

• Myers C

  Univ. Utah Ut Usa

• Yoneda T

  Soka Univ. Hachioji‐shi Jpn

• Yoneda T

  Infrastructure Systems Research Division National Institute Of Informatics

• MANNAKKARA Chammika

  National Institute of Informatics

• Myers Chris

  University Of Utah

• BEAL Frederic

  Tokyo Institute of Technology

• KITAI Tomoya

  Graduate School of Information Science and Engineering, Department of Computer Science, Tokyo Instit

• YONEDA Tomohiro

  Infrastructure Systems Research Division, National Institute of Informatics

• MERCER Eric

  Brigham Young University

• Kitai Tomoya

  Graduate School Of Information Science And Engineering Department Of Computer Science Tokyo Institut

• Wang Daihan

  National Institute Of Informatics

• HOLIMATH Vijay

  National Institute of Informatics

• OGURO Yusuke

  Graduate School of Information Science and Engineering, Dept. of Computer Science, Tokyo Institute o

• Oguro Yusuke

  Graduate School Of Information Science And Engineering Dept. Of Computer Science Tokyo Institute Of

• MERCER Eric

  Department of Electrical and Computer Engineering, University of Utah

• Myers Chris

  Department Of Electrical And Computer Engineering University Of Utah Salt Lake City

• Nanya Takashi

  University Of Tokyo

• SAITO Hiroshi

  University of Aizu

• HAMADA Naohiro

  University of Aizu

• JINDAPETCH Nattha

  Prince of Songkla University

• PRADUBSUWUN Denduang

  Tokyo Institute of Technology

• ZHOE Bin

  Cadence Design Systems

もっと見る 閉じる

著作論文

• Hazard Checking of Asynchronous Circuits : A New Approach(高信頼アルゴリズム,ディペンダブルコンピュータシステムとセキュリティ技術及び一般)
• Hazard Checking of Asynchronous Circuits: A New Approach(高信頼アルゴリズム,ディペンダブルコンピュータシステムとセキュリティ技術及び一般)
• Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation(Dependable Computing)
• Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model(Verification and Dependability Analysis)(Dependable Computing)
• Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model
• Modular Synthesis of Timed Circuits Using Partial Order Reduction
• A Conservative Framework for Safety-Failure Checking
• Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times(System Level Design,VLSI Design and CAD Algorithms)
• A Case Study on Dependable Network-on-Chip Platform for Automotive Applications
• A Case Study on Dependable Network-on-Chip Platform for Automotive Applications
• Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits(Dependable Computing)
• Comparison of standard cell based non-linear asynchronous pipelines (システムLSI設計技術・デザインガイア2007--VLSI設計の新しい大地を考える研究会)
• Framework of Timed Trace Theoretic Verification Revisited(Special Issue on Test and Verification of VLSI)
• An Online Routing Mechanism with Higher Fault-Tolerance for Network-on-Chip

もっと見る 閉じる

スポンサーリンク