Modular Synthesis of Timed Circuits Using Partial Order Reduction
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概要
- 論文の詳細を見る
This paper develops a modular synthesis algorithm for timed circuits that is dramatically accelerated by partial order reduction. This algorithm synthesizes each module in a hierarchical design individually. It utilizes partial order reduction to reduce the state space explored for the other modules by considering a single interleaving of concurrently enabled transitions. This approach better manages the state explosion problem resulting in a more than 2 order of magnitude reduction in synthesis time. The improved synthesis time enables the synthesis of a larger class of timed circuits than was previously possible.
- 社団法人電子情報通信学会の論文
- 2002-12-01
著者
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Myers C
Univ. Utah Ut Usa
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Myers Chris
Department Of Electrical And Computer Engineering University Of Utah
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YONEDA Tomohiro
National Institute of Informatics
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MERCER Eric
Brigham Young University
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MERCER Eric
Department of Electrical and Computer Engineering, University of Utah
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Yoneda T
Soka Univ. Hachioji‐shi Jpn
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Yoneda T
Infrastructure Systems Research Division National Institute Of Informatics
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Yoneda Tomohiro
National Inst. Of Informatics Tokyo Jpn
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