Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model
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概要
- 論文の詳細を見る
- 2003-12-01
著者
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Myers C
Univ. Utah Ut Usa
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Myers Chris
Department Of Electrical And Computer Engineering University Of Utah
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YONEDA Tomohiro
National Institute of Informatics
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KITAI Tomoya
Graduate School of Information Science and Engineering, Department of Computer Science, Tokyo Instit
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YONEDA Tomohiro
Infrastructure Systems Research Division, National Institute of Informatics
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OGURO Yusuke
Graduate School of Information Science and Engineering, Dept. of Computer Science, Tokyo Institute o
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MERCER Eric
Brigham Young University
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Yoneda T
Soka Univ. Hachioji‐shi Jpn
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Kitai Tomoya
Graduate School Of Information Science And Engineering Department Of Computer Science Tokyo Institut
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Oguro Yusuke
Graduate School Of Information Science And Engineering Dept. Of Computer Science Tokyo Institute Of
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Yoneda T
Infrastructure Systems Research Division National Institute Of Informatics
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- Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation(Dependable Computing)
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