Evaluation of Double Spacer Local Oxidation of Silicon (LOCOS) Isolation Process for Sub-Quarter Micron Design Rule

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Diffusion Barrier Characteristics of TiSix/TiN for Tungsten Dual Poly Gate in DRAM
Degradation of Nitride/W/WN_x/Poly-Si Gate Stack by Post-Thermal Processes
Effect of Post Thermal Processes on Nitride/W/WN_x/poly-Si Gate Stack
Impact of In Situ NH_3 Preannealing on Sub-100nm Tungsten Polymetal Gate Electrode during the Sealing Nitride Formation
Effect of Selective Oxidation Conditions on Defect Generation in Gate Oxide
Device Characteristics and Reliability of Thin Gate Dielectrics Grown by Light Wet Oxynitridation(LWO)
Effect of Gate Oxide Thickness Uniformity on the Characteristics of Three-dimensional Transistors
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ED2000-50 / SDM2000-50 Oxidation Behaviors of Ti-Polycide Gate Stack During Gate Re-oxidation
ED2000-50 / SDM2000-50 Oxidation Behaviors of Ti-Polycide Gate Stack During Gate Re-oxidation
Evaluation of Double Spacer Local Oxidation of Silicon (LOCOS) Isolation Process for Sub-Quarter Micron Design Rule
Double Spacer LOCOS Process with Shallow Recess of Silicon for 0.20μm Isolation
Evaluation of Double Spacer Local Oxidation of Silicon (LOCOS) Isolation Process for Sub-Quarter Micron Design Rule
Gate Oxide Reliability Characterization of Tungsten Polymetal Gate with Low-Contact-Resistive WSix/WN Diffusion Barrier in Memory Devices
Roles of Ti, TiN, and WN as an Interdiffusion Barrier for Tungsten Dual Polygate Stack in Memory Devices
Effect of Selective Oxidation Conditions on Defect Generation in Gate Oxide
Impact of In Situ NH3 Preannealing on Sub-100 nm Tungsten Polymetal Gate Electrode during the Sealing Nitride Formation

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