Kim Jong-choul | Memory R&d Division Hyundai Electronics Industries Co. Ltd.
スポンサーリンク
概要
関連著者
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Kim Jong-choul
Memory R&d Division Hyundai Electronics Industries Co. Ltd.
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Jang Se-aug
Memory R&d Division Hynix Semiconductor Inc.
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Cho Byung-jin
Memory R&d Division Hyundai Electronics Ind. Co. Ltd.
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KIM Jong-Choul
Memory R&D Division, Hyundai Electronics Industries Co., Ltd.
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Jang S‐a
Memory R&d Division Hynix Semiconductor Inc.
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Jang Se-aug
Memory R&d Division Hyundai Electronics Ind. Co. Ltd.
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Kim Young-bog
Memory R&d Division Hyundai Electronics Ind. Co. Ltd.
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Kim J‐c
Korea Res. Inst. Standards And Sci. Taejon Kor
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Park Young-jin
Memory R&d Division Hynix Semiconductor Co.
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Park Young-jin
Memory R&d Division Hyundai Electronics Industries Co. Ltd.
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JOO Moon-Sig
Memory R&D Division, Hynix Semiconductor Inc.
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PYI Seung-Ho
Memory R&D Division, Hynix Semiconductor Inc.
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LEE Seok-Kiu
Memory R&D Division, Hyundai Electronics Industries Co., Ltd.
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Pyi Seung-ho
Memory R&d Div. Hyundai Electronics Ind. Co. Ltd.
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Joo Moon-sig
Memory R&d Division Hynix Semiconductor Inc.
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Joo Moon-sig
Memory R&d Division Hyundai Electronics Industries Co. Ltd.
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SONG Tae-Sik
Memory R&D Div., HYUNDAI Electronics Ind. Co. Ltd.
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Lee Seok-kiu
Memory R&d Division Hyundai Electronics Industries Co. Ltd.
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Song Tae-sik
Memory R&d Div. Hyundai Electronics Ind. Co. Ltd.
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Jang Se-Aug
Memory R&D Division, HYUNDAI Electronics Ind. Co. Ltd., San 136-1, Ami-ri, Bubal-eub, Ichon, Kyungki-do,
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Kim Jong-Choul
Memory R&D Division, HYUNDAI Electronics Ind. Co. Ltd., San 136-1, Ami-ri, Bubal-eub, Ichon, Kyungki-do,
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Cho Byung-Jin
Memory R&D Division, HYUNDAI Electronics Ind. Co. Ltd., San 136-1, Ami-ri, Bubal-eub, Ichon, Kyungki-do,
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Kim Young-Bog
Memory R&D Division, HYUNDAI Electronics Ind. Co. Ltd., San 136-1, Ami-ri, Bubal-eub, Ichon, Kyungki-do,
著作論文
- Device Characteristics and Reliability of Thin Gate Dielectrics Grown by Light Wet Oxynitridation(LWO)
- Evaluation of Double Spacer Local Oxidation of Silicon (LOCOS) Isolation Process for Sub-Quarter Micron Design Rule
- Double Spacer LOCOS Process with Shallow Recess of Silicon for 0.20μm Isolation
- Evaluation of Double Spacer Local Oxidation of Silicon (LOCOS) Isolation Process for Sub-Quarter Micron Design Rule