A PLL-Based Programmable Clock Generator with 50- to 350-MHz Oscillating Range for Video Signal Processors (Special Issue on Multimedia, Analog and Processing LSIs)

概要

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A programmable clock generator, based on a phase-locked loop (PLL) circuit, has been developed with 0.5-μm CMOS triple-layer Al interconnection technology for use as an on-chip clock generator in a 300-MHz video signal processor. The PLL-based clock generator generates a clock signal whose frequency ranges from 50 to 350 MHz which is an integral multiple, from 2 to 16, of an external clock frequency. In order to achieve stable operation within this wide range, a voltage controlled oscillator (VCO) with selectable low VCO gain characteristics has been developed. Experimental results show that the clock generator generates a 297-MHz clock with a 27-MHz external clock, with jitter of 180 ps and power dissipation of 120 mW at 3.3-V power supply, and it can also oscillate up to 348 MHz with a 31.7-MHz external clock.
社団法人電子情報通信学会の論文
1994-12-25