Compact Realization of Phase-Locked Loop Using Digital Control (Special Issue on Circuit Technologies for Memory and Analog LSIs)

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概要

• 論文の詳細を見る

• This paper describes a phase-locked loop (PLL) with digital control featuring a binary quantizing circuit, a synchronizing algorithm, a lock detector and a compact D/A converter. The binary quantizing circuit and synchronizing algorithm make it possible to compare phase and frequency together and to reduce digital control logic by half. Interpolation of upper-bit D/A converter output by lower-bit output reduces the number of current sources of a 9 bit D/A converter from 511 to 80. SPICE simulation with a 0.25μm CMOS has demonstrated that the development of 200MHz PLL using digital control is feasible.

• 1997-04-25

著者

• Yamashina Masakazu

  Microelectronics Research Laboratories Nec Corporation

• Yamashina Masakazu

  Microelectronics Res. Labs. Nec Corporation

• Izumikawa M

  Microelectronics Research Laboratories Nec Corporation

• IZUMIKAWA Masanori

  Microelectronics Research Laboratories, NEC Corporation

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• A 0.18-μm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO (Special Issue on Low-Power and High-Speed LSI Technologies)
• Compact Realization of Phase-Locked Loop Using Digital Control (Special Issue on Circuit Technologies for Memory and Analog LSIs)

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