A Digital l/f Noise Generator Utilizing Probabilistic Cellular Automata
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概要
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A simple digital circuit based on the probabilistic cellular automata is proposed whose temporal evolution generates l/f noise over many frequency decades. The N cells with internal states form a one-dimensional network and probabilistically interact with nearest-neighbor ones. The internal state of the cell is either the stable state or the unstable state. Each cell obeys simple rules as follows. When the excitatory signal is applied to the cell in the stable state, the state changes to the unstable state. On the other hand, when the state is unstable, the state changes to the stable state, and then the cell generates the excitatory signal. The excitatory signal is applied to the cell which is randomly chosen between the right side cell and the left side cell. The edge condition of the network is open, so that the excitatory signal can leave both the first edge and the last edge. The excitatory signal is randomly added to the first edge of the network at intervals of T time. Then the sequential interactions may occurlike avalanche breakdown. After the interactions, the network goes to the equilibrium state. Considering that the breakdown happen simultaneously and assigning the stable state and the unstable state to 0 and 1, respectively, one can get the random pulse stream on the internal state of each cell. The power spectra of pulse streams are Lorentzian with various pole frequencies. The probability distribution of the pole frequency is inversely proportional to the frequency, i.e., obeys Zipf law. Then the total sum of the internal states of all cells fluctuates following l/f power law. The frequency range following l/f power law can be easily varied by changing the number of the cells for the summation. A prototype generator using 15 cells generates l/f noise over 3 frequency decades. This simple circuit is composed of only full adders and needs not complex components such as multipliers. Fine-tuning of any parameters and precise components also are not needed. Therefore integration into one chip using standard CMOS process is easy.
- 1998-07-25
著者
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Agu Masahiro
Department Of Media And Telecommunications Engineering Faculty Of Engineering Ibaraki University
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Agu Masahiro
Department Of Electronics Faculty Of Engineering Ibaraki University
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Yamada M
Department Of Media And Telecommunications Engineering Faculty Of Engineering Ibaraki University
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Yamada Mitsuhiro
Departmellt Of Biology C:ollegc Of Gencral Educatioll Universsity Of Tokyo
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Agu Masahiro
Department Of Electrical And Electronic Engineering Ibaraki University
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