A Sub-0.5V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation(Digital, <Special Section>Low-Power LSI and Low-Power IP)

概要

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This paper describes a speed-oriented ultralow-voltage and low-power SOI circuit technique based on a differential enhancement-and depletion-mode (ED)-MOS circuit. Combining an ED-MOS circuit block for critical paths and a multi-V_<th> CMOS circuit block for noncritical paths, that is, the so-called differential ED-CMOS/SOI circuit, makes it possible to achieve low-power and ultrahigh-speed operation of over 1 GHz at a supply voltage of less than 0.5V. As two applications of the differential ED-CMOS/SOI circuit, a multi-stage frequency divider that uses the ED-MOS circuit in a first-stage frequency divider and a pipelined adder with a CMOS pipeline register are described in detail. To verify the effectiveness of the ED-CMOS/SOI circuit scheme, we fabricated a 1/8 frequency divider and a 32-bit binary look-ahead carry (BLC) adder using the 0.25μm MTCMOS/SOI process. The frequency divider operates down to 0.3V with a maximum operating frequency of 3.6GHz while suppressing power dissipation to 0.3mW. The 32-bit adder operates at a frequency of 1GHz at 0.5V.
社団法人電子情報通信学会の論文
2005-04-01