Experimental Demonstration of Capacitor-Coupled Resonant Tunneling Logic Gates for Ultra-short Gate-delay Operation
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概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2003-11-15
著者
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水谷 照吉
愛知工業大学電気工学科
-
Ohno Y
Jst‐presto Saitama Jpn
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MAEZAWA Koichi
Graduate School of Engineering, Nagoya University
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OHNO Yutaka
Graduate School of Engineering, Nagoya University
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KISHIMOTO Shigeru
Graduate School of Engineering, Nagoya University
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MIZUTANI Takashi
Graduate School of Engineering, Nagoya University
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TANAKA Tetsuro
Graduate School of Engineering ,Nagoya University
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