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ULSI Research Laboratories, Toshiba Corporation | 論文
- Two Correlated Mechanisms in Thin SiO_2 Breakdown
- Reliability of Structurally Modified Ultra-Thin Gate Oxides
- Observation of Oxide-Thickness-Dependent Interface Roughness in Si MOS Structure
- Observation of Oxide Thickness Dependent Interface Roughness in Si MOS Structure
- Double-Level Cu Inlaid Interconnects with Simultaneously Filled Via Plugs
- A New Reverse Base Current (RBC) of the Bipolar Transistor Induced by Impact Ionization
- Gate Current Control Method by Pull-Down FET's for 0-28dB GaAs Variable Attenuator in Direct-Conversion Modulator IC for 1.9GHz PHS (Special Issue on Microwave and Millimeterwave High-power Devices)
- A Buried-Channel WN_x/W Self-Aligned GaAs MESFET with High Power-Efficiency and Low Noise-Figure for Single-Chip Front-End MMIC in Personal Handy Phone System
- Buried-Channel WN_x/W Self-Aligned GaAs MESFET Process with Selectively Implanted Channel and Undoped Epitaxial Surface Layers for MMIC Applications
- Scatterings of Shallow Threshold Voltage on Si-Implanted WN Self-Alignment Gate GaAs Metal-Semiconductor Field-Effect Transistors on Different Composition 2-Inch Substrates by Growing in Three Kinds of Furnaces
- Effects of Mask Line-and-Space Ratio in Replicating near-0.1-μm Patterns in X-Ray Lithography
- Sub-0.15 μm Pattern Replication Using a Low-Contrast X-Ray Mask
- Analysis of Sub-0.15 μm Pattern Replication in Synchrotron Radiation Lithography
- Folded Bitline Architecture for a Gigabit-Scale NAND DRAM (Special Issue on Circuit Technologies for Memory and Analog LSIs)
- Open/Folded Bit-Line Arrangement for Ultra-High-Density DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- Standby/Active Mode Logic for Sub-1-V Operating ULSI Memory (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- Anomalous Junction Leakage Behavior of Ti Self Aligned Silicide Contacts on Ultra-Shallow Junctions
- Anomalous Junction Leakage Behavior of Ti-SALICIDE Contacts on Ultra-Shallow Junctions
- A High-Performance 0.05 μm SOI MOS FET:Possibility of Velocity Overshoot
- A High Performance 0.05μm MOSFET with Thin SOI/Buried Oxide Structure