Double-Level Cu Inlaid Interconnects with Simultaneously Filled Via Plugs
スポンサーリンク
概要
- 論文の詳細を見る
- 1996-02-01
著者
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Tamura H
Tokyo Inst. Technol. Tokyo Jpn
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MINAMIHABA Gaku
ULSI Research Laboratories, TOSHIBA Corporation
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IIJIMA Tadashi
ULSI Research Laboratories, TOSHIBA Corporation
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SHIMOOKA Yoshiaki
ULSI Research Laboratories, TOSHIBA Corporation
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TAMURA Hitoshi
ULSI Research Laboratories, TOSHIBA Corporation
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KAWANOUE Takashi
ULSI Research Laboratories, TOSHIBA Corporation
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HIRABAYASHI Hideaki
Manufacturing Engineering Research Center, TOSHIBA Corporation
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SAKURAI Naoaki
Manufacturing Engineering Research Center, TOSHIBA Corporation
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OHKAWA Hideki
Manufacturing Engineering Research Center, TOSHIBA Corporation
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OBARA Takashi
Manufacturing Engineering Research Center, TOSHIBA Corporation
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EGAWA Hidemitu
Semiconductor Division, TOSHIBA Corporation
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IDAKA Toshiaki
Semiconductor Division, TOSHIBA Corporation
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KUBOTA Takeshi
Semiconductor Division, TOSHIBA Corporation
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SHIMIZU Toshio
Semiconductor Division, TOSHIBA Corporation
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KOYAMA Mitsutoshi
Semiconductor Division, TOSHIBA Corporation
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OOSHIMA Jiro
Semiconductor Division, TOSHIBA Corporation
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SUGURO Kyoichi
ULSI Research Laboratories, TOSHIBA Corporation
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Ooshima Jiro
Semiconductor Division Toshiba Corporation
関連論文
- Double-Level Cu Inlaid Interconnects with Simultaneously Filled Via Plugs
- Optimization of a High-Performance Chemically Amplified Positive Resist for Electron-Beam Lithography
- Formation of Single-Crystal Al Interconnection by In Situ Annealing
- Inlaid Cu Interconnects Employing Ti-Si-N Barrier Metal for ULSI Applications
- Double-Level Cu Inlaid Interconnects with Simultaneously Filled Via Plugs