Standby/Active Mode Logic for Sub-1-V Operating ULSI Memory (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

概要

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New gate logics, standby/active mode logic I and II, for future 1 G/4 Gb DRAM's and battery operated memories are proposed. The circuits realize sub-1-V supply voltage operation with a small 1-μA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic I is composed of logic gates using dual threshold voltage (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic II uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic I is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic II is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic.
社団法人電子情報通信学会の論文
1994-05-25