スポンサーリンク
Starc | 論文
- A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint(Test)(Dependable Computing)
- A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
- New Nondestructive Carrier Profiling for Ion Implanted Si Using Infrared Spectroscopic Ellipsometry
- Rambus DRAMを主記憶に採用したマルチメディア指向RISCプロセッサ
- マルチメディアプロセッサのRambus DRAMコントローラ
- システムLSIに輝かしい未来はあるか?
- 90nm GenericロジックCMOSプロセスを用いたメモリアレイ0.5V動作Asymmetric Three-Tr. Cell(ATC) DRAMの提案(VLSI回路, デバイス技術(高速・低電圧・低消費電力))
- 90nm GenericロジックCMOSプロセスを用いたメモリアレイ0.5V動作Asymmetric Three-Tr. Cell(ATC) DRAMの提案(VLSI回路, デバイス技術(高速・低電圧・低消費電力))
- A Test State Reduction Method for FSMs with Non-Scan DFT Using Don't Care Inputs Identification Technique (特集:システムLSIの設計技術と設計自動化)
- Two Test Generation Methods Using a Compacted Test Table and a Compacted Test Plan Table for RTL Data Path Circuits(Special Issue on Test and Verification of VLSI)
- Determination of Interconnect Structural Parameters for Best-and Worst-Case Delays(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance(Interconnect, VLSI Design and CAD Algorithms)
- A Study of Capture-Safe Test Generation Flow for At-Speed Testing
- ACS-1-2 高次ΔΣDAC信号発生回路での歪キャンセル・ノイズ低減技術(ACS-1.最新アナデジ混載LSI技術,シンポジウムセッション)
- C-12-33 最低可動電圧(V_)の低いフリップフロップ回路トポロジーの探索(C-12.集積回路,一般セッション)
- ACS-1-2 高次ΔΣDAC信号発生回路での歪キャンセル・ノイズ低減技術(ACS-1.最新アナデジ混載LSI技術,シンポジウムセッション)
- Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation(Interconnect,VLSI Design and CAD Algorithms)
- Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills(Interconnect, VLSI Design and CAD Algorithms)
- 低振幅低雑音入出力バッファ回路