スポンサーリンク
Renesas Design Corp. | 論文
- Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
- A Fast Characterizing Method for Large Embedded Memory Modules on SoC(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures(Interconnect, VLSI Design and CAD Algorithms)
- Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults
- Impact of Self-Heating in Wire Interconnection on Timing
- An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
- Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
- Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation(Interconnect,VLSI Design and CAD Algorithms)
- Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics
- Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills(Interconnect, VLSI Design and CAD Algorithms)
- A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills(VLSI Design Technology and CAD)
- A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance
- Impact of Well Edge Proximity Effect on Timing